Method of intergrating mems device with low-resistivity silicon substrates

ABSTRACT

A method of integrating MEMS devices with non-MEMS circuitry requires fabricating non-MEMS devices on a substrate in a conventional fashion. A thick dielectric layer is deposited on the completed devices, and the MEMS devices fabricated on the dielectric layer. Vias through the dielectric layer interconnect the MEMS devices to the non-MEMS electronics. The interposed dielectric layer allows the common substrate to have characteristics that best suit the non-MEMS components, without degrading the MEMS performance. Another approach involves bonding together two separate wafers—one for the MEMS devices and one for non-MEMS electronics. A package lid, having filled vias formed therethrough, is bonded to the MEMS wafer, sealing the MEMS devices within. The non-MEMS wafer is mounted to the lid, with the vias effecting the necessary interconnections between the two wafers. This enables the MEMS devices and the non-MEMS electronics to function as a single IC, while retaining the established processes associated with each component type.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to integrated circuit (IC) fabricationmethods, and particularly to methods of integratingmicroelectromechanical system (MEMS) devices with low-resistivitysilicon substrates.

[0003] 2. Description of the Related Art

[0004] Microelectromechanical system (MEMS) devices such as MEMSswitches have found a wide applicability, due to their very low loss andlow power characteristics, as well as their ability to operate at RFfrequencies. These characteristics make MEMS devices ideal for use inportable communications equipment. For example, MEMS switches and/orvariable capacitors are well-suited for use in digital tunable filtershaving low-loss and high-Q factors.

[0005] Experience with present-day MEMS devices indicates that theyperform best when built on a substrate material having a very highresistivity (>10,000 Ω-cm), as substrates having a lower resistivitytend to degrade RF performance. Unfortunately, high resistivitysubstrates are often not compatible with circuitry which isinterconnected to the MEMS devices. For example, the silicon-germanium(SiGe) BiCMOS fabrication process enables major portions of an RFtransceiver to be built on a common substrate. However, SiGe is alow-resistivity substrate material, which makes integration with MEMSdevices difficult or impractical. This typically results in the SiGecircuitry and the MEMS devices being fabricated independently onseparate substrates, which are then packaged together in a hybridstructure. While functional, hybrid packages are typically larger, moreexpensive, and less reliable than ICs.

SUMMARY OF THE INVENTION

[0006] Two methods of integrating MEMS devices with other, non-MEMScircuitry are presented. The methods overcome the problems noted above,providing smaller, cheaper and more reliable devices than werepreviously possible.

[0007] One method, referred to as “direct integration”, constructs theMEMS device(s) and the non-MEMS circuitry on a common substrate.Non-MEMS components are fabricated on a substrate in a conventionalfashion. A thick dielectric layer, preferably polyimide, is deposited onthe completed components, and the MEMS device(s) fabricated on thedielectric layer. The dielectric layer provides the high resistivityneeded for superior RF MEMS performance, while the layer's thicknessreduces parasitic capacitance and enables low-loss transmission lines tobe fabricated. Vias through the dielectric layer interconnect the MEMSdevices to the non-MEMS electronics. The presence of the interposeddielectric layer allows the common substrate to have the characteristicsthat best suit the non-MEMS components, without degrading the MEMSperformance.

[0008] Another approach, referred to as “wafer level interconnect”,involves bonding together two separate wafers—one for the MEMS device(s)and one for the non-MEMS electronics. A package lid is prepared whichwill encapsulate the MEMS devices; vias are formed through the lid andbackfilled with a conductive material. The lid is bonded to the MEMSwafer, and hermetically seals all the MEMS devices on the wafer. Thewafer holding the non-MEMS electronics is mounted to the side of the lidopposite the MEMS wafer, with the vias effecting the necessaryinterconnections between the two wafers. This enables the MEMS devicesand the other electronics to function as a single IC, while retainingthe established processes associated with each component type.

[0009] Further features and advantages of the invention will be apparentto those skilled in the art from the following detailed description,taken together with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1a is a plan view of a MEMS device directly integrated withother devices on a common substrate.

[0011]FIG. 1b is a cross-sectional view corresponding to the plan viewof FIG. 1a.

[0012]FIG. 2a is a plan view of a preferred direct integration of a MEMSdevice with other devices on a common substrate.

[0013]FIG. 2b is a cross-sectional view corresponding to the plan viewof FIG. 2a.

[0014]FIG. 3a is a plan view of a device formed by a first method fromcomponents fabricated on two different substrates.

[0015]FIG. 3b is a cross-sectional view corresponding to the plan viewof FIG. 3a.

[0016]FIG. 4a is a plan view of a device formed by a second method fromcomponents fabricated on two different substrates.

[0017]FIG. 4b is a cross-sectional view corresponding to the plan viewof FIG. 4a.

DETAILED DESCRIPTION OF THE INVENTION

[0018] An IC structure which integrates MEMS devices with other,non-MEMS devices on a common substrate is depicted in FIGS. 1a (planview) and 1 b (corresponding cross-sectional view), respectively. Asused herein, a “non-MEMS device” is any device, such as a transistor,resistor, capacitor, etc., which does not include a moving member. Suchdevices are formed on a substrate 12 in a conventional manner.

[0019] In accordance with the present invention, one or more MEMSdevices are integrated with devices 10 by first depositing a layer ofoxide 14 on top of substrate 12 to protect the existing devices. Adielectric layer 16 is deposited on oxide layer 14, on which one or moreMEMS devices 18 is formed. To interconnect the MEMS devices with devices10, vias 20 are formed through dielectric layer 16 and oxide layer 14.Metallization 22 is then deposited, patterned, and etched to fill thevias and provide the necessary interconnections.

[0020] The dielectric layer 16 provides several characteristicsimportant to the proper performance of MEMS devices 18. Layer 16provides a smooth surface, which aids in the proper operation of sometypes of MEMS devices, such as capacitive membrane switches, due totheir device geometries. Dielectric layer 16 also provides ahigh-resistivity substrate, which, as noted above, is needed for theproper operation of RF MEMS devices. To prevent RF performancedegradation, the resistivity of dielectric layer 16 ispreferably >10,000 Ω-cm.

[0021] Dielectric layer 16 is also preferably thick, i.e., ≧15 μm, andhas a dielectric constant k which is ≦3. This enables transmission linesformed on the surface of dielectric layer 16 to be made wide, whichreduces parasitic capacitance and makes the lines low-loss. A dielectriclayer of, for example, polyimide, can provide the desirablecharacteristics noted above.

[0022] With dielectric layer 16 imposed between non-MEMS devices 10 andMEMS devices 18, substrate 12 can have characteristics which best suitdevices 10 without degrading the performance of the MEMS devices. Forexample, substrate 12 can have a low-resistivity, such as a SiGesubstrate (10-20 Ω-cm), which is well-suited to use with high frequencytransistors. The use of dielectric layer 16 negates what might otherwisebe the adverse affect of a low-resistivity substrate on MEMS devices 18.

[0023] A preferred implementation of a directly integrated structure perthe present invention is shown in FIGS. 2a and 2 b (plan andcorresponding cross-sectional views, respectively). As before, non-MEMSdevices 10 are supported by substrate 12, and protected with an oxidelayer 14. To support RF MEMS device operation, a metal ground planelayer 30 is fabricated on oxide layer 14. Dielectric layer 16 resides ontop of ground plane layer 30, and a layer of oxide 32 is deposited ontop of dielectric layer 16 to provide a smooth, planar surface whichsupports high quality MEMS fabrication.

[0024] One or more MEMS devices 18 are fabricated on oxide layer 32, andvias 34 are formed through oxide layers 32 and 14, dielectric layer 16,and ground plane layer 30. Metallization 22 is then deposited,patterned, and etched to fill the vias and provide the necessaryinterconnections between MEMS devices 18 and non-MEMS devices 10fabricated on substrate 12. As noted above, dielectric layer 16 issuitably polyimide which is ≧15 μm thick, has a dielectric constant kwhich is ≦3, and a resistivity of >10,000 Ω-cm.

[0025] For best performance, the completed device should be encapsulatedwithin a package that hermetically seals the device inside the packagecavity.

[0026] Another method of forming a single device which combines MEMSdevices and non-MEMS devices is shown in FIGS. 3a (plan view) and 3 b(corresponding cross-sectional view). Here, MEMS devices 50 arefabricated on a first substrate 52, through which vias 54 have beenformed for connection to, for example, a printed circuit board (PCB) 56.A package lid 58 is prepared which will encapsulate the MEMS devices;vias 59 are formed through the lid and backfilled with a conductivematerial. Lid 58 has a seal area 60 which contacts substrate 52 and arecessed area 62 where the MEMS devices reside. Lid 58 is bonded tosubstrate 52, thereby covering and preferably hermetically sealing theMEMS devices within. Vias 59 align with solder bumps 65 on the MEMSsubstrate to provide interconnections through the lid. The lid ispreferably glass, such as Pyrex or quartz, because it has a coefficientof thermal expansion about equal to silicon.

[0027] The chemical makeup of glass is well-suited to its use as a lid.The chemical makeup of glass facilitates the anodic bonding of the lid58 to the substrate 52, as it sets up an electrostatic attractionbetween the silicon and the lid so that molecular sealing takes place.This is accomplished by, for example, applying a large negativepotential to glass lid 58 once it is in contact with substrate 52. Thepositive sodium ions in the glass are drawn to the large negativepotential, creating a strong attraction between the glass and thesilicon at the substrate surface.

[0028] One or more non-MEMS devices 66, such as high frequencytransistors, are fabricated on a second substrate 68. When fabricationof the non-MEMS devices is completed, substrate 68 is bonded to the sideof lid 58 opposite substrate 52, preferably using surface mounttechnology (SMT) techniques. Interconnections between non-MEMS devices66, MEMS devices 50, and PCB 56 are provided by vias 59 through the lid,vias 54 through substrate 52, and solder bumps or balls as needed. Forexample, solder balls 70 may be used to bond substrate 68 to lid 58.Solder balls 72 may also be used to attach and interconnect substrate 52to PCB 56—preferably using SMT techniques though many other methods areavailable for attaching a substrate to a PCB.

[0029] Lid 58 is prepared by, for example, starting with a glass blockhaving the proper outer dimensions, and etching recessed area 62 fromthe center of the block. The recessed area is then surrounded by araised gridwork that is attached to a seal ring on MEMS substrate 52.Attachment is then made by anodic bonding.

[0030] This approach allows both the MEMS devices 50 and the non-MEMSdevices 66 to be fabricated on their respective preferred substrates.For example, devices 66 may require a low-resistivity substrate such asSiGe for proper operation, and MEMS devices 50 may need ahigh-resistivity substrate to support RF operation. This is permitted bythe present method, which allows each substrate to be independentlyselected to meet the needs of the devices it will support.

[0031] An alternative method of combining two different substrates intoa single device is shown in FIGS. 4a (plan view) and 4 b (correspondingcross-sectional view). As in FIG. 3, one or more MEMS devices 80 arefabricated on a substrate 82, through which vias 83 are formed. A lid84, preferably glass, having a recessed area 86 and a seal area 88, isaffixed to substrate 82 such that MEMS devices 80 are encapsulatedwithin. As above, lid 84 is preferably anodically bonded to substrate82, such that a hermetic seal is provided.

[0032] One or more non-MEMS devices 90 are fabricated on a secondsubstrate 92. Here, however, rather than mount substrate 92 to theopposite side of lid 84, substrate 92 is flipped over and affixeddirectly to the bottom of substrate 82 using, for example, solder balls94. Interconnection points on substrate 92 are aligned with vias 83, sothat interconnections between MEMS devices 80 and non-MEMS devices 90are made using the vias.

[0033] As with the approach shown in FIG. 3, this approach allows theMEMS devices 80 and the non-MEMS devices 90 to be fabricated on theirrespective preferred substrates, such as a low-resistivity substrate(e.g., SiGe) for non-MEMS devices 90, and a high-resistivity substratefor the MEMS devices. Each substrate may be independently selected tomeet the needs of the devices it will support.

[0034] Please note that, while FIGS. 1-4 depict the integration of oneMEMS device with one non-MEMS device, the invention would typically beemployed to combine numerous MEMS and non-MEMS devices into a singledevice.

[0035] While particular embodiments of the invention have been shown anddescribed, numerous variations and alternate embodiments will occur tothose skilled in the art. Accordingly, it is intended that the inventionbe limited only in terms of the appended claims.

We claim:
 1. A method of directly integrating microelectromechanicalsystem (MEMS) devices and non-MEMS devices on a common substrate,comprising: fabricating at least one non-MEMS device on a substrate,depositing a layer of oxide on said substrate, depositing a dielectriclayer on said oxide layer, fabricating at least onemicroelectromechanical system (MEMS) device on said dielectric layer,patterning and etching vias through said dielectric layer, anddepositing, patterning and etching a metal layer which interconnects atleast one of said MEMS devices to at least one of said non-MEMS deviceson said substrate.
 2. The method of claim 1, wherein said substrate is alow-resistivity substrate.
 3. The method of claim 2, wherein saidlow-resistivity substrate comprises silicon-germanium (SiGe).
 4. Themethod of claim 1, wherein said dielectric layer is polyimide.
 5. Themethod of claim 1, wherein said dielectric layer is ≧15 μm thick and hasa dielectric constant k which is ≦3.
 6. The method of claim 1, whereinsaid dielectric layer has a resistivity of >10,000 Ω-cm.
 7. The methodof claim 1, further comprising depositing a metal ground plane layer onsaid oxide layer prior to depositing said dielectric layer.
 8. Themethod of claim 1, further comprising depositing a second oxide layer onsaid dielectric layer prior to fabricating said MEMS devices.
 9. Amethod of directly integrating microelectromechanical system (MEMS)devices and non-MEMS devices on a low-resistivity substrate, comprising:fabricating at least one non-MEMS device on a low-resistivity substrate,depositing a first oxide layer on said low-resistivity substrate,depositing a metal ground plane layer on said first oxide layer,depositing a dielectric layer which is ≧15 μm thick, has a dielectricconstant k which is ≦3, and has a resistivity of >10,000 Ω-cm on saidfirst oxide layer, depositing a second oxide layer on said dielectriclayer, fabricating at least one microelectromechanical system (MEMS)device on said second oxide layer, patterning and etching vias throughsaid dielectric layer and said oxide layers, and depositing, patterningand etching a metal layer which interconnects at least one of said MEMSdevices to at least one of said non-MEMS devices on said low-resistivitysubstrate.
 10. The method of claim 9, wherein said low-resistivitysubstrate comprises silicon-germanium (SiGe).
 11. The method of claim 9,wherein said dielectric layer is polyimide.
 12. An integrated devicestructure which includes at least one microelectromechanical system(MEMS) device and at least one non-MEMS device fabricated on a commonsubstrate, comprising: a substrate on which at least one non-MEMS deviceis fabricated, an oxide layer on said substrate, a dielectric layer onsaid oxide layer, at least one microelectromechanical system (MEMS)device on said dielectric layer, at least one via through saiddielectric layer, and metallization which interconnects at least one ofsaid MEMS devices with at least one of said non-MEMS devices on saidsubstrate via said at least one via.
 13. The integrated device structureof claim 12, wherein said substrate is a low-resistivity substrate. 14.The integrated device structure of claim 13, wherein saidlow-resistivity substrate comprises silicon-germanium (SiGe).
 15. Theintegrated device structure of claim 12, wherein said dielectric layeris polyimide.
 16. The integrated device structure of claim 12, whereinsaid dielectric layer is ≧15 μm thick and has a dielectric constant kwhich is ≦3.
 17. The integrated device structure of claim 12, whereinsaid dielectric layer has a resistivity of >10,000 Ω-cm.
 18. Theintegrated device structure of claim 12, further comprising a metalground plane layer between said oxide layer and said dielectric layer.19. The integrated device structure of claim 12, further comprising asecond oxide layer between said dielectric layer and said MEMS devices.20. An integrated device structure which includes microelectromechanicalsystem (MEMS) devices and non-MEMS devices fabricated on alow-resistivity substrate, comprising: a low-resistivity substrate onwhich at least one non-MEMS device is fabricated, a first oxide layer onsaid low-resistivity substrate, a metal ground plane layer on said firstoxide layer, a dielectric layer on said first oxide layer which is ≧15μm thick, has a dielectric constant k which is ≦3, and has a resistivityof >10,000 Ω-cm, a second oxide layer on said dielectric layer, at leastone microelectromechanical system (MEMS) device on said second oxidelayer, at least one via through said dielectric layer and said oxidelayers, and metallization which interconnects at least one of said MEMSdevices with at least one of said non-MEMS devices on saidlow-resistivity substrate via said at least one via.
 21. The integrateddevice structure of claim 20, wherein said low-resistivity substratecomprises silicon-germanium (SiGe).
 22. The integrated device structureof claim 20, wherein said dielectric layer is polyimide.
 23. A method offorming a device which includes microelectromechanical system (MEMS)devices and non-MEMS devices fabricated on respective substrates,comprising: fabricating at least one microelectromechanical system(MEMS) device on a first substrate, preparing a lid for encapsulatingsaid MEMS devices, said preparation including providing vias throughsaid lid and backfilling said vias with a conductive material, bondingsaid lid to said first substrate such that said lid encapsulates saidMEMS devices, fabricating at least one non-MEMS device on a secondsubstrate, and bonding said second substrate to the side of said lidopposite said first substrate such that at least one of said non-MEMSdevices on said second substrate is interconnected to at least one ofsaid MEMS devices via at least one of said vias.
 24. The method of claim23, wherein said second substrate is a low-resistivity substrate. 25.The method of claim 24, wherein said second substrate comprisessilicon-germanium (SiGe).
 26. The method of claim 23, wherein said firstsubstrate has a high resistivity.
 27. The method of claim 26, whereinsaid first substrate has a resistivity of >10,000 Ω-cm.
 28. The methodof claim 23, wherein said lid is bonded to said first substrate usinganodic bonding.
 29. The method of claim 23, wherein said lidhermetically seals said MEMS devices.
 30. The method of claim 23,wherein said lid is glass.
 31. The method of claim 23, wherein saidsecond substrate is bonded to said lid using surface-mount technology.32. The method of claim 23, further comprising forming vias through saidfirst substrate and filling said vias with a conductive material suchthat, when mounted to a printed circuit board (PCB), said vias throughsaid first substrate interconnect said device to said PCB.
 33. A methodof forming a device which includes microelectromechanical system (MEMS)devices and non-MEMS devices fabricated on respective substrates,comprising: forming vias through a high-resistivity substrate andfilling said vias with a conductive material, fabricating at least oneMEMS device on said high-resistivity substrate, preparing a lid forencapsulating said MEMS devices, said preparation including providingvias through said lid and backfilling said vias with a conductivematerial, anodically bonding a glass lid to said high-resistivitysubstrate which hermetically seals said MEMS devices, fabricating atleast one non-MEMS device on a low-resistivity substrate, and surfacemounting said low-resistivity substrate to the side of said lid oppositesaid high-resistivity substrate such that at least one of said non-MEMSdevices on said low-resistivity substrate is interconnected to at leastone of said MEMS devices via at least one of said vias.
 34. The methodof claim 33, wherein said low-resistivity substrate comprisessilicon-germanium (SiGe).
 35. The method of claim 33, further comprisingmounting said device to a printed circuit board (PCB) such that saidvias through said first substrate interconnect said device to said PCB.36. A device which includes microelectromechanical system (MEMS) devicesand non-MEMS devices fabricated on respective substrates, comprising: afirst substrate on which at least one MEMS device is fabricated, a lidbonded to said first substrate which encapsulates said MEMS devices, atleast one via through said lid, each of said vias filled with aconductive material, and a second substrate on which at least onenon-MEMS device is fabricated, said second substrate bonded to the sideof said lid opposite said first substrate such that at least one of saidMEMS devices is interconnected to at least one of said devices on saidsecond substrate via at least one of said vias.
 37. The device of claim36, wherein said lid is glass.
 38. The device of claim 36, wherein saidlid is anodically bonded to said first substrate.
 39. The device ofclaim 36, wherein said lid hermetically seals said MEMS devices.
 40. Thedevice of claim 36, wherein said first substrate has a resistivityof >10,000 Ω-cm.
 41. The device of claim 36, wherein said secondsubstrate comprises silicon-germanium (SiGe).
 42. The device of claim36, wherein said first substrate further comprises vias filled with aconductive material such that, when said device is mounted to a printedcircuit board (PCB), said vias through said first substrate interconnectsaid device to said PCB.
 43. A device which includesmicroelectromechanical system (MEMS) devices and non-MEMS devicesfabricated on respective substrates, comprising: a high-resistivitysubstrate on which at least one MEMS device is fabricated and whichincludes at least one via therethrough, said at least one via filledwith a conductive material, a glass lid anodically bonded to said firstsubstrate which hermetically seals said MEMS devices, at least one viathrough said lid, each of said vias backfilled with a conductivematerial, and a low-resistivity substrate on which at least one non-MEMSdevice is fabricated, said low-resistivity substrate bonded to the sideof said lid opposite said high-resistivity substrate such that at leastone of said MEMS devices is interconnected to at least one of saidnon-MEMS devices on said high-resistivity second substrate via at leastone of said vias.
 44. The device of claim 43, wherein saidlow-resistivity substrate comprises silicon-germanium (SiGe).
 45. Thedevice of claim 43, wherein said high-resistivity substrate has aresistivity of >10,000 Ω-cm.
 46. The device of claim 43, furthercomprising a printed circuit board (PCB), said device mounted to saidPCB such that said at least one via through said first substrateinterconnects said device to said PCB.
 47. A method of forming a devicewhich includes microelectromechanical system (MEMS) devices and non-MEMSdevices fabricated on respective substrates, comprising: forming one ormore vias through a first substrate and filling said vias with aconductive material, fabricating at least one MEMS device on said firstsubstrate, bonding a lid which encapsulates said MEMS devices to saidfirst substrate, fabricating at least one non-MEMS device on a secondsubstrate, and bonding said second substrate to the side of said firstsubstrate opposite said lid such that at least one of said non-MEMSdevices on said second substrate is interconnected to at least one ofsaid MEMS devices via at least one of said vias.
 48. The method of claim47, wherein said second substrate is surface mounted to said firstsubstrate.
 49. The method of claim 47, wherein said lid is anodicallybonded to said first substrate.
 50. The method of claim 47, wherein saidlid hermetically seals said MEMS devices.
 51. The method of claim 47,wherein said first substrate has a resistivity of >10,000 Ω-cm.
 52. Themethod of claim 47, wherein said second substrate comprisessilicon-germanium (SiGe).
 53. A device which includesmicroelectromechanical system (MEMS) devices and non-MEMS devicesfabricated on respective substrates, comprising: a first substratethrough which at least one via is formed, each of said vias filled witha conductive material, at least one MEMS device fabricated on said firstsubstrate, a lid bonded to said first substrate which encapsulates saidMEMS devices, and a second substrate on which at least one non-MEMSdevice is fabricated, said second substrate bonded to the side of saidfirst substrate opposite said lid such that at least one of said MEMSdevices is interconnected to at least one of said non-MEMS devices onsaid second substrate via at least one of said vias.
 54. The device ofclaim 53, wherein said lid is glass.
 55. The device of claim 53, whereinsaid lid is anodically bonded to said first substrate.
 56. The device ofclaim 53, wherein said lid hermetically seals said MEMS devices.
 57. Thedevice of claim 53, wherein said first substrate has a resistivityof >10,000 Ω-cm.
 58. The device of claim 53, wherein said secondsubstrate comprises silicon-germanium (SiGe).
 59. A device whichincludes microelectromechanical system (MEMS) devices and non-MEMSdevices fabricated on respective substrates, comprising: ahigh-resistivity substrate through which at least one via is formed,each of said vias filled with a conductive material, at least one MEMSdevice fabricated on said high-resistivity substrate, a glass lidanodically bonded to said first substrate which hermetically seals saidMEMS devices, and a low-resistivity substrate on which at least onenon-MEMS device is fabricated, said low-resistivity substrate bonded tothe side of said high-resistivity substrate opposite said lid such thatat least one of said MEMS devices is interconnected to at least one ofsaid non-MEMS devices on said high-resistivity substrate via at leastone of said vias.
 60. The device of claim 59, wherein saidhigh-resistivity substrate has a resistivity of >10,000 Ω-cm.
 61. Thedevice of claim 59, wherein said low-resistivity substrate comprisessilicon-germanium (SiGe).